What this is
A Network-on-Chip is how cores, caches, and memory controllers on the same die communicate: packets routed hop by hop through a network of routers instead of competing for a single shared bus.
This project is a synthesizable SystemVerilog implementation of a packet-switched NoC, designed to stand on its own as a reusable IP block and eventually serve as the communication fabric for a multicore SoC.
Architecture (locked)
- 5-port mesh, XY/DOR routing
- 2 virtual channels per port
- Credit-based flow control
- 4-flit input buffers
- Two-stage round-robin arbitration
These architectural choices have been evaluated and are currently frozen. The goal is to establish a fixed baseline for RTL implementation and verification rather than continuously redesigning the network.
The router pipeline is:
BW → VA → SA → ST → LT
Lookahead routing computation is folded into BW so that a flit does not spend an additional cycle determining where it needs to go.
Router components
- Input FIFO — implemented and testbenched
- Arbitration — architecture under evaluation
- Input port cluster — BW, RC, per-VC control
- Crossbar
- VA / SA
- Output pipeline — ST, LT
Open Questions
Some architectural questions are intentionally left open until the relevant design work forces a decision. These are not implementation gaps; they are the problems currently being reasoned through.
VA/SA sequencing Should virtual-channel allocation wait for switch arbitration, or proceed speculatively? The former adds a dependency; the latter risks reserving resources for flits that ultimately lose arbitration.
Local port placement In a dimension-sliced crossbar, where does the Local port belong? North, South, East, and West naturally map onto dimensions. Local does not.
Link traversal How much of link traversal can occur concurrently with the preceding switch stage, and what must wait for the next cycle?
VC allocation for coherence traffic Are two VCs sufficient for deadlock avoidance alone, or should coherence message classes be separated as well? These address different forms of interference, but compete for the same VC budget.
AXI4-Stream to credit-based flow control Where should the protocol boundary live between a PE using AXI4-Stream and a network using credits, and how should backpressure be represented across that boundary?